Today, with rapid development of science and technology, liquid crystal displays have been widely applied in electronic display products such as televisions, computers, mobile phones and personal digital assistances and so on. A liquid crystal display comprises a source driver, a gate driver, a liquid crystal display panel and so on. A pixel array is disposed on the liquid crystal display panel, the gate driver is configured to select respective pixel rows in the pixel array sequentially, so as to transmit pixel data outputted from the source driver to respective pixels in the pixel row currently selected by the gate driver, thus displaying an image to be displayed.
At present, the gate driver is formed on an array substrate of the liquid crystal display by a process of array, that is, a process of Gate Driver on Array GOA, such that cost may be saved and a beautiful design with two symmetric sides may be achieved for the panel. In addition, bonding area and fan-shaped wiring space for a gate Integrated Circuit IC may be omitted, such that a narrow frame design may be achieved, meanwhile a bonding process in the direction of gate scanning may be omitted, which is advantageous for the increasing of productivity and yield rate.
The gate driver is commonly constituted by a plurality of shift registers connected in cascade, driving signal output terminals of the respective shift registers correspond to respective gate lines respectively so as to output scan signals to the respective gate lines in a scanning direction sequentially. Particularly, structure of a shift register is shown in FIG. 1, and the shift register comprises an input unit 01, a reset unit 02, a node control unit 02, a pull-up unit 04, a pull-down unit 05, an input signal terminal Input, a reset signal terminal Reset, a first clock signal terminal ck and a reference signal terminal Vref. An output terminal of the input unit 01, an output terminal of the reset unit 02, a first terminal of the node control unit 03 and a control terminal of the first pull-up unit 04 are connected to a first node PU, a second terminal of the node control unit 03 and a control terminal of the first pull-up unit 05 are connected to a second node PD; an output terminal of the first pull-up unit 04 and an output terminal of the first pull-down unit 05 are connected to a driving signal output terminal Out of the shift register. In the shift register shown in FIG. 1, the input unit 01 is configured to control a level at the first node PU under a control of the input signal terminal Input, the reset unit 02 is configured to control the level at the first node PU under a control of the reset signal terminal Reset, the node control unit 03 is configured to control the level at the first node PU and a level at a second node PD, the first pull-up unit 04 is configured to supply a signal at the first clock signal terminal ck1 to the driving signal output terminal Output under a control of the first node PU, the first pull-down unit 5 is configured to supply a signal at the reference signal terminal Vref to the driving signal output terminal Out under a control of the second node PD.
At present, the shift register at each of respective stages in the gate driver in the display panel is generally as shown in FIG. 1, the display panel outputs scan signals to respective gate lines through the shift registers at respective stages in the scanning direction sequentially, With increasing of resolution of display product, a power consumption of the display panel also increases, rendering standby time of the display product is decreased hugely. Therefore, how to reduce power consumption of the display product to increase the standby time becomes an urgent technical problem to be solved for those skilled in the art.